1. Field of the Invention
The present invention relates generally to a semiconductor memory device and operation methods thereof. More specifically, the present invention relates to a single-poly non-volatile memory (NVM) device. The single-poly NVM device according to this invention, which is compatible with standard CMOS fabrication processes, has the advantages of low power consumption, high write/erase efficiency, improved data retention, and high packing density.
2. Description of the Prior Art
Electronic memory comes in a variety of forms to serve a variety of purposes. Flash anderasable programmable read only memory (EPROM) are used for easy and fast information storage in such devices as personal digital assistants (PDA), digital cameras and home video game consoles. Generally, an EEPROM chip has a grid of columns and rows with a cell that has two transistors at each intersection. One of the transistors is known as a floating gate, and the other one is the control gate. The floating gate's only link to the row, or word line, is through the control gate. As long as this link is in place, the cell has a value of 1. Changing the value to a 0 requires a well-known process called Fowler-Nordheimtunneling or hot carrier injection. It is often desirable to combine many functions on a single device, also called as system-on-a-chip (SOC), to reduce the number and cost of chips. Embedding NVM in a CMOS device allows a single chip produced by a manufacturer to be configured for a variety of applications, and/or allows a single device to be configured by a user for different applications. To combine with standard CMOS process flow, single-poly NVM devices have been developed.
An important property of non-volatile memories is the data retention, which is defined as the time during which the written information is still present to a sufficient degree at the floating gate. In general, the leakage current which causes the electric charge to disappear from the floating gate should be so small that the memory can remain in use without rewriting during a period of several years, for example, ten years. Continued device scaling demands that gate oxide layer becomes thinner and thinner. However, thin gate oxide layer deteriorates the loss of electric charge at the floating gate owing to tunneling of electrons from the floating gate to the substrate.
FIG. 1 is a schematic, cross-sectional view of a prior art single-poly NVM cell 10.
As shown in FIG. 1, the NVM cell 10 comprises an NMOS structure 28 and a PMOS structure 30. Field oxide layer 24 isolates the PMOS structure 30 from the NMOS structure 28. The NMOS structure 28 is formed on a P-type substrate 12 and comprises an NMOS gate 32, an N+ source region 14, and an N+ drain region 16. The PMOS structure 30 is formed on an N-well 18 and comprises a PMOS floating gate 34, a P+ source region 20, and a P+ drain region 22. A channel stop region 38 is obliquely implanted underneath the PMOS floating gate 34 for facilitating band-to-band hot electron injection into the PMOS floating gate. A conductor 36 directly electrically couples the NMOS gate 32 to the PMOS floating gate 34. That is, there is a conductive current path from one gate to the other, as opposed to indirectly coupling, such as capacitively coupling. Both gates 32 and 34 are floating, that is, they are not directly electrically coupled to a voltage or current source or sink on the IC, and at the same electrical potential. The conductor may be a polysilicon trace formed at the same time as the gates, or may be a metal or silicide conductor formed later in the fabrication sequence.
However, the above described prior art NVM cell 10 suffers from several drawbacks. First, the prior art NVM cell 10 consumes a lot of chip area since it is composed of a PMOS structure 30 and a NMOS structure 28, and the extra field oxide layer 24 is needed for isolating the PMOS 30 form the NMOS 28. Second, the prior art NVM cell 10 needs an extra channel stop region 38 and formation of conductor 36 for connecting two gates, this, in turns, means extra process steps and thus raised cost.